Because copper has a lower resistivity and higher resistance to electromigration compared to aluminum, it has become the preferred material for creating conductive lines in high performance integrated circuits. Since Cu does not readily form volatile compounds and is therefore difficult to dry etch, the fabrication of Cu interconnects requires a damascene approach, whereby a metal is deposited into a recess etched in an insulating material (dielectric) and then planarized using chemical mechanical polish (CMP). While the damascene concept is straightforward and has been used for centuries in jewelry making, etc., the fabrication of damascene Cu interconnects in integrated circuits is a challenging task due to problems associated with Cu integrations.
One integration issue is that Cu can readily diffuse into surrounding oxide-like or polymeric dielectric materials when subjected to high temperatures of subsequent fabrication processes. Diffusion of Cu into the surrounding insulating dielectric will lead to line-to-line leakages and eventual device failure. So it is necessary to fully enclose Cu lines with diffusion barriers. FIG. 1 illustrates a cross section of a part of a damascene device in which a Cu line 101 is encapsulated by metal diffusion barriers 105, typically made of tantalum, tantulum nitride or combination thereof, between the Cu and surrounding dielectric material 107. In addition, a dielectric capping layer 103 is deposited between the Cu line 101 and dielectric 109 to avoid electrical shorting of adjacent metal lines and to complete the Cu encapsulation. The dielectric capping layer material is typically silicon nitride because of its ability to block Cu diffusion and resist the dielectric etches used to define subsequent vias to the overlying metal level. Prior to deposition of the dielectric capping layer, the copper oxide that has formed on the surface of the Cu (Cu readily oxidizes when exposed to water or air) must be removed by chemical reduction to promote adhesion and optimize device reliability.
Another integration issue when using Cu as the primary conductor in devices is that Cu can easily electromigrate into the surrounding dielectric material. In general, electromigration occurs when the metal atoms of conductive lines are subjected to electric fields while the circuit is in operation. The metal atoms will redistribute in the direction of the electron flow to form voids (areas lacking metal material) and extrusions (protrusions of metal material outside of the metal or dielectric barrier) along the length of the metal lines. For example, this is illustrated in damascene device of FIG. 1. A void 111 has formed at the silicon nitride/Cu interface, causing the Cu buildup and formation of an extrusion 113 downstream of the electron flow 115 in the Cu line 101. Voids will cause the Cu line to thin and eventually separate completely, causing an open circuit. Extrusions can cause the Cu metal to extend past the Cu line into an adjacent Cu line, thereby causing a short circuit.
Although silicon nitride as a capping layer material is effective in blocking Cu diffusion, there are some problems of using a silicon nitride capping layer, especially related to the electromigration issues described above. For example, it has been observed that voids caused by electromigration (described above) are observed most frequently at the edges of the Cu lines at the silicon nitride/Cu interface. This is likely partly due to the poor adhesion between silicon nitride and Cu. Furthermore, once a void is formed, the area around the void will experience increased electron flux, causing even more pronounced electromigration and acceleration of the degradation process. Another issue with using silicon nitride as a capping layer is that silicon nitride has a relatively high dielectric constant. This means that when a layer of silicon nitride is directly on top of and adjacent to the Cu conductive lines, there is an increase in overall capacitance between the conductive lines, which increases the RC time delay.
Because of the problems associated with using silicon nitride, others have proposed using other materials for capping Cu lines. For example, Saito, et al (0-7803-6679-4/01, 2001 IEEE) has studied the preferential deposition of tungsten to cap Cu lines. One reason for this is because tungsten adheres well to Cu. In addition, tungsten has a relatively low resistivity compared to silicon nitride.
There are other integration issues, however, associated with using tungsten and other refractory metals for capping of Cu lines. Since a refractory metal is more conductive than silicon nitride, it must be selectively deposited over copper lines with minimal coverage over the insulating regions of the device. It is also important that the refractory metal be deposited conformally and particle-free so that there is good contact between Cu and the capping layer. This uniform and selective deposition of a refractory metal can be difficult to achieve. In a single-step process certain areas of the substrate will start to nucleate before other areas. The film will then start to grow in these regions first, leading to a large uncontrolled non-uniformity. In some cases the regions that started growing first will get thick, thereby causing adjacent areas of the substrate to loose selectivity.
What is therefore needed is a process for forming a selective refractory metal capping layer that obviates these and other problems.